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3-1 tm file number 3652.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 HSP50210 digital costas loop the digital costas loop (dcl) performs many of the baseband processing tasks required for the demodulation of bpsk, qpsk, 8-psk, oqpsk, fsk, am and fm waveforms. these tasks include matched ?tering, carrier tracking, symbol synchronization, agc, and soft decision slicing. the dcl is designed for use with the hsp50110 digital quadrature tuner to provide a two chip solution for digital down conversion and demodulation. the dcl processes the in-phase (i) and quadrature (q) components of a baseband signal which have been digitized to 10 bits. as shown in the block diagram, the main signal path consists of a complex multiplier, selectable matched ?ters, gain multipliers, cartesian-to-polar converter, and soft decision slicer. the complex multiplier mixes the i and q inputs with the output of a quadrature nco. following the mix function, selectable matched ?ters are provided which perform integrate and dump or root raised cosine ?tering ( ~ 0.40). the matched ?ter output is routed to the slicer, which generates 3-bit soft decisions, and to the cartesian-to- polar converter, which generates the magnitude and phase terms required by the agc and carrier tracking loops. the pll system solution is completed by the HSP50210 error detectors and second order loop filters that provide carrier tracking and symbol synchronization signals. in applications where the dcl is used with the hsp50110, these control loops are closed through a serial interface between the two parts. to maintain the demodulator performance with varying signal power and snr, an internal agc loop is provided to establish an optimal signal level at the input to the slicer and to the cartesian-to-polar converter. features clock rates up to 52mhz selectable matched filtering with root raised cosine or integrate and dump filter second order carrier and symbol tracking loop filters automatic gain control (agc) discriminator for fm/fsk detection and discriminator aided acquisition swept acquisition with programmable limits lock detector data quality and signal level measurements cartesian to polar converter 8-bit microprocessor control - status interface designed to work with the hsp50110 digital quadrature tuner 84 lead plcc applications satellite receivers and modems bpsk, qpsk, 8-psk, oqpsk, fsk, am and fm demodulators digital carrier tracking related products: hsp50110 digital quadrature tuner, d/a converters hi5721, hi5731, hi5741 hsp50110/210eval digital demod evaluation board block diagram data path multiplexer filter control interface status 10 13 track control out(9-0) out(9-0) bus track control rrc dump integrate/ loop filter magnitude phase i q 10 8 8 carrier acq/trk loop filter symbol q i level detect hi/lo slicer cartesian to polar filter rrc dump integrate/ nco level detect cos sin 10 10 carrier control/ tracking 3 3 8 8 lock detect serclk (cof) (sof) a b smblclk thresh lkint oea oeb symbol i ser or i in (9-0) carrier phase error detect loop filter symbol phase detect error or clk q ser or q in (9-0) data sheet january 1999
3-2 pinout 84 lead plcc top view 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 aout4 aout5 aout6 gnd aout7 aout8 aout9 oea thresh sloclk hi/lo iser qser vcc ssync gnd serclk iin9 iin8 iin7 iin6 gnd lkint fz-ct fz-st cof c0 c1 vcc c2 c3 c4 c5 c6 c7 a0 a1 gnd a2 rd wr cofsync iin5 iin4 iin3 iin2 gnd iin1 iin0 sync qin9 qin8 qin7 qin6 qin5 qin4 vcc qin3 qin2 qin1 qin0 sofsync sof aout1 aout3 aout2 aout0 smblclk vcc clk gnd bout9 bout8 bout7 bout6 bout5 gnd bout4 bout2 bout1 bout0 oeb vcc bout3 ordering information part number temp. range ( o c) package pkg. no. HSP50210jc-52 0 to 70 84 lead plcc n84.1.15 HSP50210ji-52 -40 to 85 84 lead plcc n84.1.15 HSP50210 3-3 pin description name type description v cc - +5v power supply. gnd - ground. iin9-0 i in-phase parallel input. data may be two s complement or offset binary format (see table 14). these inputs are sampled by clk when the sync signal is active low. iin9 is the msb. see input controller section. qin9-0 i quadrature parallel input. data may be two s complement or offset binary format (see table 14). these inputs are sampled by clk when the sync signal is active low. qin9 is the msb. see input controller section. sync i data sync. when sync is asserted ?ow? data on iin9-0 and qin9-0 is clocked into the processing pipeline by the rising edge of clk. cof o carrier offset frequency. the frequency term generated by the carrier tracking loop filter is output serially via this pin. the new offset frequency is shifted out msb ?st by clk or sloclk starting with the clock cycle after the assertion of cofsync. cofsync o carrier offset frequency sync. this signal is asserted one clk or sloclk cycle before the msb of the serial data word. (programmable polarity, see table 41, bit 11). sof o sampler offset frequency. sample frequency correction term generated by the symbol tracking loop filter is output serially via this pin. the frequency word is shifted out msb ?st by clk or sloclk starting with the clock cycle after assertion of sofsync. sofsync o sampler offset frequency sync. this signal is asserted one clk or sloclk cycle before the msb of the serial data word. (programmable polarity, see table 41, bit 12). a2-0 i address bus. the address on these pins specify a target register for reading or writing (see microprocessor interface section). a0 is the lsb. c7-0 i/o microprocessor interface data bus. this bi-directional bus is used for reading and writing to the processor interface. these are the data i/o pins for the processor interface. c0 is the lsb. wr i write. this is the write strobe for the processor interface (see microprocessor interface section). rd i read. this is the read enable for the processor interface (see microprocessor interface section). fz_st i freeze symbol tracking loop. asserting this pin ?igh zeroes the sampling error into the symbol tracking loop filter (see symbol tracking loop filter section). fz_ct i freeze carrier tracking loop. asserting this pin ?igh zeroes the carrier phase error input to the carrier tracking loop filter. lkint o lock detect interrupt. this pin is asserted ?igh for at least 4 clk cycles when the lock detector integration cycle is ?ished (see lock detector section). used as an interrupt for a processor. the lock detect interrupt may be asserted ?igh?longer than 4 clk cycles, depending on the lock detector mode. thresh o threshold exceeded. this output is asserted ?ow when the magnitude out of the cartesian to polar converter exceeds the programmable power detect threshold (see table 15 and agc section). sloclk o slow clock. optional serial clock used for outputting data from the carrier and symbol tracking loop filters. the clock is programmable and has a 50% duty cycle. note: not used when the hsp50110 is used with the HSP50210 (see table 41). iser i in-phase serial input. serial data input for in-phase data. data on this pin is shifted in msb ?st and is synchronous to serclk (see input controller section). qser i quadrature serial input. serial data input for quadrature data. data on this pin is shifted in msb ?st and is synchronous to serclk (see input controller section). ssync i serial word sync. this input is asserted ?igh?one clk before the ?st data bit of the serial word (see figure 2). serclk i serial clock. may be asynchronous to other clocks. used to clock in serial data (see input controller section). aout9-0 o a output. data on this output depend on the configuration of output selector. aout9 is the msb (see table 42). bout9-0 o b output. data on this output depend on the configuration of output selector. bout9 is the msb (see table 42). smblclk o symbol clock. 50% duty cycle clock aligned with soft bit decisions (see figure 19). oea i a output enable. this pin is the three-state control pin for the aout9-0. when oea is high, the aout9-0 is high impedance. oeb i b output enable. this pin is the three-state control pin for the bout9-0. when oeb is high, the aout9-0 is high impedance. hi/lo 0 hi/lo. the output of the input level detector is provided on this pin (see input level detector section). this signal can be externally averaged and used to control the gain of an ampli?r to close an agc loop around the a/d converter. this type of agc sets the level based on the median value on the input. clk i system clock. asynchronous to the processor interface and serial inputs. HSP50210 3-4 cos sin synthesizer/ nco mixer tan -1 ( ) i 2 +q 2 q i carrier phase error detect cartesian slicer 2nd order loop filter carrier tracking loop filter gain error detect agc level detect lock input controller frequency error detect d dt discriminator m u x m u x m u x m u x rrc m u x m u x symbol phase error detect symbol tracking matched filtering to polar detect i&d acquisition control from lock detector iin9-0 qin9-0 sof sofsync cof cofsync sloclk microprocessor interface 8 c7-0 wr rd hi/lo thresh aout9-0 bout9-0 lkint serclk iser qser ssync serial output formatter i&d 2nd order loop filter sync rrc a2-0 clk oea oeb smblclk frz_st frz_ct q i figure 1. functional block diagram of the HSP50210 HSP50210 3-5 functional description the HSP50210 digital costas loop (dcl) contains most of the baseband processing functions needed to implement a digital costas loop demodulator. these functions include lo generation/mixing, matched ?tering, agc, carrier phase and frequency error detection, timing error detection, carrier loop ?tering, bit sync loop ?tering, lock detection, acquisition/tracking control, and soft decision slicing for forward error correction algorithms. while the dcl is designed to work with the hsp50110 digital quadrature tuner (dqt) as a variable rate psk demodulator for satellite demodulation, functions on the chip are common to many communications receivers. the dcl provides the processing blocks for the three tracking loops commonly found in a data demodulator: the automatic gain control (agc) loop, the carrier tracking loop, and a symbol tracking loop. the agc loop adjusts for input signal power variations caused by path loss or signal-to-noise variations. the carrier tracking loop removes the frequency and phase uncertainties in the carrier due to oscillator inaccuracies and doppler. the symbol tracking loop removes the frequency and phase uncertainties in the data and generates a recovered clock synchronous with the received data. each loop consists of an error detector, a loop ?ter, and a frequency or gain adjustment/control. the agc loop is internal to the dcl, while the symbol and carrier tracking loops are closed external to the dcl. when the dcl is used together with the hsp50110, the tracking loops are closed around the baseband ?tering to center the signal in the ?ter bandwidth. in addition, the agc function is divided between the two chips with the hsp50110 providing the coarse agc, and the HSP50210 providing the ?e or ?al agc. a top level block diagram of the HSP50210 is shown in figure 1. this diagram shows the major blocks and the multiplexers used to recon?ure the data path for various architectures. input controller in-phase (i) and quadrature (q) data enters the part through the input controller. the 10-bit data enters in either serial or parallel fashion using either two s complement or offset binary format. the input mode and binary format is set in the data path con?uration control register, bits 14 and 15 (see table 14). if parallel input mode is selected, i and q data are clocked into the part through iin0-9 and qin0-9 respectively. data enters the processing pipeline when the input enable ( sync) is sampled ?ow by the processing clock (clk). the enable signal is pipelined with the data to the various processing elements to minimize pipeline delay where possible. as a result, the pipeline delay through the agc, carrier tracking, and symbol tracking loop filters is measured in clks; not input data samples. if serial input mode is selected, the i and q data enters via the iser and qser pins using serclk and ssync. the beginning of a serial word is designated by asserting ssync ?igh?one serclk prior to the ?st data bit, as shown in figure 2. on the following serclk s, data is shifted into the register until all 10 bits have been input. data shifting is then disabled and the contents of the register are held until the next assertion of ssync. the assertion of a ssync transfers data into the processing pipeline, and the shift register is enabled to accept new data on the following serclk. when data is transferred to the processing pipeline by ssync, a processing enable is generated which follows the data through the pipeline. this enable allows the delay through processing elements (like the loop ?ters) to be minimized since their pipeline delay is expressed in clks not ssync periods. note: ssync should not be asserted for more than one serclk cycle. input level detector the input level detector generates a one-bit error signal for an external if agc ?ter and ampli?r. the error signal is generated by comparing the magnitude of the input samples to a user programmable threshold. the hi/lo pin is then driven ?igh?or ?ow?depending on the relationship of its magnitude to the threshold. the sense of the hi/lo pin is programmable so that a magnitude exceeding the threshold can either be represented as a ?igh?or ?ow?logic state. the input level detector (hi/lo output) threshold and the sense are set by the data path con?uration control register bits 16-23 and 13 (see table 14). note: the input level detector is typically not used in applications which use the HSP50210 with the hsp50110. the high/low outputs can be integrated by an external loop ?ter to close an agc loop. using this method, the gain of the loop forces the median magnitude of the input samples to the threshold. when the magnitude of half of the samples is above the threshold (and half is below), the error signal is integrated to zero by the loop ?ter. the magnitude of the complex input is estimated by: iser/ msb msb serclk ssync qser ote: data must be loaded msb ?st. igure 2. serial input timing for iser and qser inputs ssync leads 1st data bit mag (i, q) i 0.375 q if i q and > + = mag (i, q) q 0.375 i if q i > + = (eq. 1) HSP50210 3-6 complex multiply m u x r e g r e g r e g r e g r e g r e g sin cos 15 tap rrc 15 tap rrc r e g r e g r e g r e g m u x l i m i t r e g r e g r e g r e g r e g ? dump ? dump r e g m u x m u x cartesian to nco mixer matched filtering root raised cosine (rrc) integrate and dump bypass rrc bypass mixer bypass polar iin9-0 qin9-0 d e m u x soft decision slicer d e m u x r e g i end i mid q end q mid to carrier tracking and discriminator to symbol tracking data de-skew oqpsk mid and end symbol samples agc threshold thresh agc error detect ? hold agc loop gain mantissa s h i f t loop gain exponent l i m i t upper gain limit lower gain limit r e g agc loop filter o u t p u t s e l e c t r e g r e g aout9-0 bout9-0 + + m u x m u x r e g + + i&d r e g r e g r e g r e g - + r e g r e g m u x compare r e g tan -1 ( ) i 2 +q 2 q i 5 delay reg 5 delay reg m u x threshold power phase out at @ or mag out at @ or ! ! or ! or * * * @ or ! @ @ reg reg reg reg sin/cos rom reg + reg cf register from carrier tracking loop filter reg reg level detect hi / lo register enable rate @ = sync rate = twice symbol rate ! = symbol rate blank = clk rate * @ @ ** * + m u x test r e g r e g r e g s h i f t s h i f t false lock compare reg two sample summer error gain figure 3. main data path 8 8 HSP50210 3-7 nco/mixer the nco/mixer performs a complex multiply between the baseband input and the output of a quadrature nco (numerically controlled oscillator). when the HSP50210 (dqt) is used with the hsp50110 (dcl), the nco/mixer shortens the carrier tracking loop (i.e., minimizes pipeline delay around the loop) while providing wide loop bandwidths. this becomes important when operating at symbol rates near the maximum range of the part. there are three con?urations possible for closing the carrier tracking loop when the dqt and the dcl are used together. the ?st con?uration utilizes the nco on the dqt and bypasses the nco in the dcl. the data path con?uration control register (see table 14), bit 10, and carrier loop filter control register #1 (see table 20), bit 6, are used to bypass the dcl nco/mixer and route the loop ?ter outputs, respectively. the dqt provides maximum ?xibility in nco control with respect to frequency and phase offsets. the second con?uration feeds the lead carrier loop ?ter term to the dcl nco/mixer, and the lag loop ?ter term to the dqt nco. this reduces the loop transport delay while maintaining wide loop bandwidths and reasonable loop damping factors. this con?uration is especially useful in satcom applications with medium to high symbol rates. the carrier loop filter control register #1, bit 5, is where the lead/lag destination is set. the ?al con?uration feeds both the lead and lag carrier loop filter terms back to the dcl nco/mixer. this provides the shortest transport delay. the dcl nco/mixer provides only for frequency/phase control from the carrier loop ?ter. the center frequency of this nco/mixer is set to the average of the upper and lower carrier loop limits programmable parameters. these parameters are set in the two control registers bearing their names (see tables 22 and 23). the nco/mixer uses a complex multiplier to multiply the baseband input by the output of a quadrature nco. this operation is represented by: equation 3 illustrates how the complex multiplier implicitly performs the summing function when the dcl is con?ured as a modulator. the quadrature outputs of the nco are generated by driving a sine/cosine look-up table with the output of a phase accumulator as shown in figure 3. each time the phase accumulator is clocked, its sum is incremented by the contents of the carrier frequency (cf) register. as the accumulator sum increments from 0 to 2 32 , the sin/cos rom produces quadrature outputs whose phase advances from 0 to 360 o . the cf register contains a 32-bit phase increment which is updated with the output of carrier tracking loop. large phase increments take fewer clocks to step through the sine wave cycle, which results in a higher frequency nco output. the cf register sets the nco frequency with the following equation: where f clk is the clk frequency, and cf is the 32-bit two s complement hexadecimal value loaded into the carrier frequency register. as an example, if the cf register is loaded with a value of 4000 0000 (hex), and the clk frequency is 40mhz, the nco would produce quadrature terms with a frequency of 10mhz. when cf is a negative value, a clockwise cos/sin vector rotation is produced. when cf is positive, a counterclockwise vector rotation is produced. note: the nco is set to a xed frequency by programming the upper and lower limits of the carrier tracking loop filter to the same value and zeroing the lead gain. matched filtering the HSP50210 provides two selectable matched ?ters: a root raised cosine filter (rrc) and an integrate and dump (i&d) ?ter. these are shown in figure 3. the rrc ?ter is provided for shaped data pulses and the i&d ?ter is provided for square wave data. the ?ters may be cascaded for better adjacent channel rejection for square wave data. if these two ?ters do not meet baseband ?tering requirements, then they can be bypassed and an external digital ?ter (such as the hsp43168 dual fir filter or the hsp43124 serial i/o filter) used to implement the desired matched ?ter. the desired ?ter con?uration is set in the data path con?uration control register, bits 1-7 (see table 14). the sample rate of the baseband input depends on the symbol rate and ?tering con?uration chosen. in con?urations which bypass both ?ters or use only the rrc filter, the input sample rate must be twice the symbol rate. in con?urations which use the i&d filter, the input sample rate is decimated by the i&d filter, down to two samples per symbol. i&d con?urations support input sample rates up to 32 times the input symbol rate. the rrc ?ter is a ?ed coef?ient 15 tap fir ?ter. it has ~40% excess bandwidth beyond nyquist which equates to = ~0.4 shape factor. the ?ter frequency response is shown in figure 4 and figure 5. in addition, the 9-bit ?ter coef?ients are listed as integer values in table 1. the noise equivalent bandwidth of the rrc ?ter and other ?ter con?urations possible with the hsp50110/210 chipset are given in appendix a. i out i in c () cos q in c () sin = q out i in c () sin q in c () cos + = (eq. 2) (eq. 3) f c f clk cf () 2 ? 32 = cf int f c f clk ? () 2 32 [] h = (eq. 4) HSP50210 3-8 the i&d ?ter consists of an accumulator, a programmable shifter and a two sample summer as shown in figure 3. the programmable shifter is provided to compensate for the gain introduced by the accumulator (see table 14). the accumulator provides integrate and dump filtering for decimation factors up to 16. the two sample summer provides the moving average required for an additional decimation factor of 2. a decimation factor of 1 (bypass), 2, 4, 8, 16, or 32 may be selected. at the maximum decimation rate, a baseband signal sampled at 32 times the symbol rate can be ?tered. the output of the two sample summer is demultiplexed into two sample streams at the symbol rate. the demultiplexed data streams from the i and q processing paths are fed to the symbol tracking block and soft decision slicer. the multiplexed data streams on i and q are provided as one of the selectable inputs for the cartesian to polar converter. cartesian/polar converter the cartesian/polar converter maps samples on the i and q processing paths to their equivalent phase/magnitude representation. the magnitude conversion is equivalent to: where 0.81 is the gain of the conversion process. the magnitude output is an 8-bit unsigned value ranging from 0.0 to 1.9922. 0 -20 -40 -60 -80 -100 0 f clk frequency (normalized to input sample rate) normalized magnitude (db) figure 4. rrc filter in HSP50210 10 2f clk 10 3f clk 10 4f clk 10 f clk 2 0 -0.18 -0.36 -0.54 -0.72 -0.90 0 -0.07 -0.14 -0.21 -0.28 -0.35 0 frequency (normalized to input sample rate) f clk 25 2f clk 25 3f clk 25 4f clk 25 f clk 5 figure 5. passband ripple of rrc filter in HSP50210 normalized magnitude (db) normalized magnitude (db) shown below enlarged for clarity 0 f clk 40 f clk 20 3f clk 40 f clk 10 3f clk 20 5f clk 40 table 1. root raised cosine coefficients coefficient index coefficient 02 1-2 21 38 4 -16 5 -14 686 7 160 886 9 -14 10 -16 11 8 12 1 13 -2 14 2 mag (i, q) 0.81 () ? i 2 q 2 + () , = (eq. 5) HSP50210 3-9 the phase conversion is equivalent to: where tan -1 ( ) is the arctangent function. the phase conversion output is an 8-bit two s complement output which ranges from -1.0 to 0.9922 (80 to 7f hex, respectively). the -1 to almost 1 range of the phase output represents phase values from - to , respectively. an example of the i/q to phase mapping is shown in figure 6. the phase and magnitude values may be output via the output selector bits 0-3 (see table 42). the i/q data path selected for input to the cartesian to polar converter determines the input data rate of the agc and carrier tracking loops. if the i/q data path out of the integrate and dump filter is selected, the agc is fed with magnitude values produced by the end-symbol samples. magnitude values produced by midsymbol samples are not used because these samples occur on symbol transitions, resulting in poor signal magnitude estimates. the carrier tracking block is fed with phase values generated from both the end and mid-symbol samples. the carrier tracking loop filter, however, is only fed with phase error terms generated by the end symbol samples. if the input of the i&d is selected for input to the coordinate converter, the control loops are fed with data at the i/q data rate. the desired data path input to the cartesian to polar converter is specified in the data path configuration control register, bit 8 (see table 14). agc the agc loop operates on the main data path (i and q) and performs three signal level adjusting functions: 1) maximizing dynamic range, 2) compensating for snr variations, and 3) maintaining an optimal level into the soft decision slicer. the agc loop block diagram, shown in figure 7, consists of an error detector, a loop filter, and signal gain adjusters (multipliers). the agc error detector generates an error signal by subtracting the programmable agc threshold from the magnitude output of the cartesian to polar converter. this difference signal is scaled (gain adjusted via multiplier and shifter), then ?tered (integrated) by the agc loop filter to generate the gain correction to the i and q signals at the multipliers. if a ?ed gain is desired, set the upper and lower limits equal. the agc responds to the magnitude of the sum of all the signals in the bandpass of the narrowest ?ter preceding the cartesian to polar coordinate converter. this ?ter may be the integrate and dump ?ter shown in figure 8, the rrc ?ter upstream in the HSP50210 data path, or some other ?ter outside the dcl chip. the magnitude signal usually contains several components: 1) the signal of interest component, 2) the noise component, and 3) interfering signals component. at high snr s the signal of interest is signi?antly greater than the other components. at lower snr s, components 2 or 3 may become greater than the signal of interest. narrowing the filter bandwidth is the primary technique used to mitigate magnitude contributions of component 3. this will also improve the snr by reducing the magnitude contributions of element 2. consideration of the range of signal amplitudes expected into the HSP50210, in conjunction with a gain distribution analysis, will provide the necessary insight to set the signal level into the soft decision slicer to yield optimum performance. note: failure to consider the variations due to noise or interfering signals, can result in signal limiting in the HSP50210 processing algorithms, which will degrade the system bit error rate performance. figure 6a. i input to cartesian/polar converter figure 6b. q input to cartesian/polar converter figure 6c. car tesian/polar converter phase output phase (i, q) tan 1 qi ? () , = (eq. 6) 0.5 0 -0.5 1.0 -1.0 - 0 /2 - /2 input phase magnitude 0.5 0 -0.5 1.0 -1.0 - 0 /2 - /2 input phase magnitude 0.5 0 -0.5 1.0 -1.0 - 0 /2 - /2 input phase output voltage HSP50210 3-10 the agc loop is con?ured by the power detect threshold and agc loop parameters control registers (see tables 15 and 16). seven programmable parameters must be set to con?ure the agc loop and its status outputs. two parameters, the power threshold and the agc threshold are associated with the error detector and are represented in 8-bit fractional unsigned binary format: 2 0 .2 -1 2 -2 2 -3 2 -4 2 - 5 2 -6 2 -7. . while the format provides a range from 0 - 1.9961 for the thresholds, the cartesian to polar converter scales the i and q input magnitudes by 0.81. thus, if a full scale ( 1) complex (i and q) input signal is presented to the converter, the output will be (0.81) 2 + (0.81) 2 = 1.1455. the agc threshold parameter value is the desired magnitude of the signal as it enters the soft decision slicer. it is the parameter that will determine the error signal in the agc loop. the power threshold, on the other hand, determines only the power threshold at which the thresh signal is asserted. if the signal magnitude exceeds the threshold, then the thresh is asserted. this may be used for signal detection, power detection or external agc around the a/d converter. the agc threshold parameter is set in the agc loop parameters control register, bits 16-23 (see table 16). the power threshold parameter is set in the power detect threshold control register, bits 0-7 (see table 15). note that these two threshold parameters are not required to be set to identical or even related values, since they perform independent functions the enable agc parameter sets the agc error detector output to zero if asserted and to normal error detection output when not asserted. this control bit is set in the agc loop parameter control register, bit 31 (see table 16). this bit is used to disable the agc loop. the remaining agc parameters determine the agc loop characteristics: gain tracking, tracking rate and tracking limits. the agc loop gain is set via two parameters: agc loop gain exponent and agc loop gain mantissa. in general, the higher the loop gain, the faster signal level acquisition and tracking, but this must be tempered by the specific signal characteristics of the application and the remaining programmable loop parameters. for the HSP50210, the agc loop gain provides for a variable attenuation of the input to the loop filter. the agc gain mantissa is a 4-bit value which provides error signal scaling from 0.000 to 0.9375, with a resolution of 0.0625. table 2 details the discrete set of decimal values possible for the agc loop gain mantissa. the exponent provides a shift factor scaling from 2 -7 to 2 -14 . table 3 details the discrete set of decimal values possible for the agc loop gain exponent. when combined, the exponent and mantissa provide a loop gain defined as: where m is a binary number with a range from 0 to 15 and e is a 3-bit binary value from 0 to 7. m and e are the parameters set in the agc loop parameters control register, bits 24-30 (see table 16). the composite range of the agc loop gain is 0.0000 to [0.9375][2-7]. this will scale the agc error signal to a range of 0.000 to (1.1455)(0.9375)(2-7) = 1.07297(2-7). table 2. agc loop gain binary mantissa to decimal scaled mantissa mapping binary code (mmmm) decimal scaled mantissa binary code (mmmm) decimal scaled mantissa 0000 0.0000 1000 0.5000 0001 0.0625 1001 0.5625 0010 0.1250 1010 0.6250 0011 0.1875 1011 0.6875 0100 0.2500 1100 0.7500 0101 0.3125 1101 0.8125 0110 0.3750 1110 0.8750 0111 0.4375 1111 0.9375 table 3. agc loop binary exponent to scaled decimal exponent mapping binary code (eee) decimal/ hex exponent decimal scaled exponent 000 0 2 -7 001 1 2 -8 010 2 2 -9 011 3 2 -10 100 4 2 -11 101 5 2 -12 110 6 2 -13 111 7 2 -14 agc loop gain: g agc m () 2 4 () [] 2 7e + () () [] = (eq. 7) HSP50210 3-11 the agc loop filter integrates the scaled error signal to provide a correction control term to the multipliers in the i and q path. the loop filter accumulator has internal upper and lower limiters. the upper eight bits of the accumulator output map to an exponent and mantissa format that is used to set these upper and lower limits. the format, illustrated in figure 8, is used for the agc upper limit, agc lower limit and the correction control term (agc output). this format should not be confused with the similar format used for the agc loop gain. the input to the agc loop filter is included in figure 8 to show the relative weighting of the input to output of the loop filter. the loop filter input is represented as the eleven letter ??. lower case ??and ??detail the format for the agc upper and lower limits. this change in type case should help keep the agc limits and agc gain formats from being confused. the agc upper and lower limits are set in the agc loop parameters control register, bits 0-15, (see table 16). this 6-bit unsigned mantissa format provides for an agc output control range from 0.0000 to 0.9844, with a resolution of 0.015625. the 2-bit exponent format provides an agc output control range from 1 to 8. the decimal values for each of the 64 binary mantissa values is detailed in table 4, while table 5 details the decimal value for the 4 exponent values. the agc output is implemented in the multiplier according to equation 8. where m and e are the binary values for mantissa and exponent found in tables 4 and 5. note:this format is identical to the format used to program the agc upper and lower limits, but in this usage it is not a pro- grammed value. it is a representation of the digital agc output number which is presented to the gain adjuster (multipliers) to correct the gain of the i and q data signals in the main data path. these equations yield a composite (mantissa and exponent) agc output range of 0.0000 to 1.9844(2 3 ) which is a logarithmic range from 0 to 24db. figure 9 has graphed the results of equation 8 for both the linear and logarithmic equations. figure 9 also has a linear estimate of the logarithmic equation. this linear approximation will be used in calculating the agc response time. l i m i t cartesian to polar agc error detect ? s h i f t l i m i t r e g agc loop filter - + r e g r e g m u x compare r e g tan -1 ( ) i 2 +q 2 q i m u x + gain error agc limit ? upper agc limit ? lower power agc thrshld ? agc loop enable agc ? gain mantissa ? agc loop gain exponent ? cart/polar input select ? read reg i&d filter i&d filter i q magnitude phase thresh gain adjust (0 - 1.1455) (0.000 to 0.9375) (2 -7 to 2 -14 ) 0.000 to 1.07297(2 -7 ) 1.0000 to 15.8572 = g agc (0 to 24db) figure 7. agc loop block diagram thrshld ? ? indicates a microprocessor control signal. agc gain = (1.0 + m) x 2 e g agc 1.0 0.8 g 1.64 2 ----------- = dcloutlvl agc thresh 1.64 2 ----------- - ?? ?? = where dcloutlvl is the magnitude output expressed in db from full scale (dbfs) out agc linear 1.0 m agc + () 2 e () = out agc db 20 log 1.0 m agc + () 2 e () [] = (eq. 8a) (eq. 8b) 2 1 2 0 .2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 ee.mmmmm m gggg gg gg gg g figure 8. agc output a nd agc limits bit weighting HSP50210 3-12 there are two techniques for setting a fixed gain for the agc. the first is to set control word 2 bit 31 = 1. this precludes any error update of present agc gain value. the second is to set the upper and lower agc limits to the desired gain using figure 9. the upper and lower limits have the same value for this case. the HSP50210 provides two mechanisms for monitoring signal strength. the first, which involved the thresh signal, has already been described. the second mechanism is via the microprocessor interface. the 8 most significant bits of the agc loop filter output can be read by a microprocessor. refer to the microprocessor interface section for details of how to read this value. this agc value has the format described in figure 8. agc bit weighting and loop response the agc loop response is a function of the programmable gain, the bit weightings inherent in the connection of each element of the loop, the agc loop ?ter limits and the magnitude of the input gain error step. table 6 details the bit weighting between each element of the agc loop from the error detector through the weighting at the gain adjuster in the signal path. the agc loop gain sets the growth rate of the sum in the loop ?ter accumulator. the loop ?ter output growth rate determines how quickly the agc loop traces the transfer function shown previously in figure 9. to calculate the rate at which the agc can adjust over a given period of time, a gain step is introduced to the gain error detector and the amount of change that is observed between clocks at the agc level adjusters (multipliers) is the agc response time in db per symbol. this agc loop will respond immediately with the greatest correction term, then asymptotically approach zero correction. we begin calculation of the loop response with a full scale error detector input of 1. this error input is scaled by the cartesian to polar converter, the error detector and the agc loop gain, accumulated in the loop filter, limited and output to the gain adjusters. the agc loop tries to make the error correction as quickly as possible, but is limited by the agc table 4. agc gain mantissa to decimal mapping binary code (mmmmmm agc ) decimal value of agc mantissa binary code (mmmmmm agc ) decimal value of agc mantissa 000000 0.000000 100000 0.500000 000001 0.015625 100001 0.515625 000010 0.031250 100010 0.531250 000011 0.046875 100011 0.546875 000100 0.062500 100100 0.562500 000101 0.078125 100101 0.578125 000110 0.093750 100110 0.593750 000111 0.109375 100111 0.609375 001000 0.125000 101000 0.625000 001001 0.140625 101001 0.640625 001010 0.156250 101010 0.656250 001011 0.171875 101011 0.671875 001100 0.187500 101100 0.687500 001101 0.203125 101101 0.703125 001110 0.218750 101110 0.718750 001111 0.234375 101111 0.734375 010000 0.250000 110000 0.750000 010001 0.265625 110001 0.765625 010010 0.281250 110010 0.781250 010011 0.296875 110011 0.796875 010100 0.312500 110100 0.812500 010101 0.328125 110101 0.828125 010110 0.343750 110110 0.843750 010111 0.359375 110111 0.859375 011000 0.375000 111000 0.875000 011001 0.390625 111001 0.890625 011010 0.406250 111010 0.906250 011011 0.421875 111011 0.921875 011100 0.437500 111100 0.937500 011101 0.453125 111101 0.953125 011110 0.468750 111110 0.968750 011111 0.484375 111111 0.984375 table 5. agc gain exponent to decimal mapping binary code decimal/ hex exponent decimal scaled exponent 00 0 2 0 01 1 2 1 10 2 2 2 11 3 2 3 data path gain (linear) gain (db) gain control word (8 msbs of loop filter accumulator) gain db 16 12 8 4 0 24 18 12 6 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 1 figure 9. gain control transfer function linear estimate in db 256 gain linear HSP50210 3-13 loop gain and potentially, the agc limits. the maximum agc response is the maximum gain adjustment made in any given clock cycle. this involves applying maximum loop gain and setting the agc limits as wide as possible. a calculation using only exponent terms of the various gains will be sufficient to yield a rough order of magnitude of the range of the agc loop response. the results are shaded in the last column of table 6 and provided in detail in equations 9a and 9b. agc response max = input (cartesian to polar converter gain)(error detector gain)(agc loop gain)(agc output weighting) agc response max = 1(0.5)(0.5)(2 -7 )(24) = 1(2 -9 )(24) = 0.04688db/symbol time where (0.5) is the msb of the 0.81 scaling in the cartesian to polar coordinate converter, (0.5) is the msb of the mantissa of the loop gain, (2 -7 ) is the maximum shift gain, and 24 is the maximum loop ?ter gain. a similar procedure is used to calculate the minimum agc response rate. agc response min = 1(0.5)(0.5)(2 -14 )(24) = 1(2 -16 )(24) = 0.000366db/symbol time thus, the expected range for the agc rate is approximately 0.0004 to 0.0469db/symbol time. table 6. agc bit weighting agc accum bit position gain error input gain error bit weight agc loop filter gain (mantissa) agc loop filter gain multiplier (output) agc loop filter gain bits kept (rnd) shift = 0 shift = 7 agc output and agc limits bit weight agc gain resolution (db) 22 shifter e1 12 21 shifter e0 6 20 multiplier m-1 3 19 m -2 1.5 18 m -3 0.75 17 m -4 0.375 16 m -5 0.1875 15 multiplier 1 m -6 0.09375 14 13 1 g -8 0.02344 12 2 g -9 0.01172 11 3 g -10 0.00586 10 4 g -11 0.00293 9 5 g -12 0.00146 8 8(s) = 1(s) 0. 12(s) 12(s) = 1 1 6 g -13 0.000732 7 7 = 0 ? x1111= 0 ? 6 6 = 1 x 10 10 = 1 1 g -15 0.000183 5 5 = 2 x 9 9 = 2 2 g -16 0.0000916 4 4 = 3 x 8 8 = 3 3 g -17 0.0000458 3 3 = 4 7 7 = 4 4 g -18 0.0000229 2 2 = 5 6 6 = 5 5 -19 0.0000114 1 1 = 6 5 5 = 6 6 -20 0.00000572 0 0 = 7 4 -21 0.00000286 3 2 1 0 0 ? ? 0-7 0.04688 0 ? g -14 0.000366 (eq. 9a) (eq. 9b) HSP50210 3-14 gain distribution the gain distribution in the dcl is shown in figure 10. these gains consist of a combination of ?ed, programmable, and adaptive gains. the ?ed gains are introduced by processing elements such as the mixer and square root of root raised cosine filter. the adaptive gains are set to compensate for variations in input signal strength. the main signal path, with processing block gains and path bit weightings, is shown in figure 10. the quadrature inputs to the HSP50210 are 10-bit fractional two s complement numbers with relative bit weightings, as shown in the figure 10. the ?st element in the processing chain is the mixer, which scales the quadrature outputs of the complex multiplier by 1/2 providing a gain of g = 0.5. if the mixer is bypassed, the signal is passed unmodi?d with a gain of 1.0. following the mixer, the quadrature signal is passed to the ?ed coef?ient rrc ?tering block, which has a gain of 1.13 if enabled and 1.0 if bypassed. next, the agc supplies gain to maintain an optimal signal level at the input to the soft decision slicer, cartesian to polar converter, and the symbol tracking loop. the gain supplied by the agc ranges from 1.0 to 1.9844*2 3 . following the agc, the signal path is limited to 8 bits and passed through the integrate and dump filter en route to the soft decision slicer and symbol tracking block. the i&d filter uses an accumulator together with a sample pair summer to achieve the desired decimation rate. the i&d shifter is provided to compensate for the gain introduced by the i&d accumulator. the accumulator introduces gain equal to the decimation factor r, and the shifter gain can be set to 1/r. for example, if the i&d filter decimation of 16 is chosen the i&d accumulator will accumulate 8 samples before dumping, which produces a gain of 8. thus, for unity gain, the i&d shifter would be set for a gain of 2 -3 . the sample pair summer is unity gain since its output is scaled by one-half. symbol tracking the symbol tracking loop adjusts the baseband sampling frequency to force sampling of the baseband waveform at optimal points for data decisions. the key elements of this loop are the sampling error detector and symbol tracking loop filter shown in figure 11. the output of these two blocks is a frequency correction term which is used to adjust the baseband sample frequency external to the HSP50210. in typical applications, the frequency correction term is fed back to the hsp50110 to adjust baseband sampling via the resampling nco (see hsp50110 datasheet). synthesizer/ g = 1.0, 0.5 (note 1) -2 0 2 -9 2 -1 mantissa 1.0 - 1.9844 (0.0156 steps) exponent 2 0 -2 3 mixer g = 1.0 - 1.9844*2 3 l i m i t sample pair summer binary agc gain part rrc filter g = 1.0, 1.13 (note 2) -2 0 2 0 2 -10 2 -1 -2 1 rnd 2 -10 2 -1 rnd 2 0 2 -9 2 -1 2 1 2 2 2 3 2 4 -2 5 -2 0 2 -7 2 -1 int/dump accumulator g = 1-16 2 -7 2 -1 2 0 2 1 2 2 2 3 -2 4 rnd int/dump shifter g = 2 0 - 2 -4 2 -11 2 -1 2 0 2 1 2 2 2 3 -2 4 -2 0 2 -6 2 -1 -2 0 2 -6 2 -1 g = 0.5, 1.0 (note 3) 2 -7 input to soft decision slicer and symbol tracking block input to cartesian to polar converter if agc output selected input to cartesian to polar converter if int/dump output selected input point integrate and l i m i t dump filter notes: 1. if the mixer is enabled the result of the complex multiply is scaled by two (g = 0.5). if the mixer is bypassed, the data pas ses unmodified (g = 1.0). 2. if the root raised cosine filter is enabled, a gain of g = 1.13 is introduced. if the rrc filters bypassed, the gain is unity . 3. if the integrate and dump filter is bypassed the sample pair summer has a gain of g = 1.0 and the 2 -7 -bit position is set to 1. if the integrate and dump is enabled, the sample pair sum is scaled by one half (g = 0.5). 4. the negative sign on the msbs indicates use of 2? complement data format. figure 10. gain distribution and intermediate bit weightings (note 4) / 8 g agc HSP50210 3-15 - + + mid-symbol transition detect data decision mid-symbol ? ?1 ? mux ? single/ double mux ? reg reg mux reg reg lead mantissa acq lead mantissa track lead exponent acq lead exponent track zero lead sampling error detector frz_st ? mux ? reg reg reg reg lag mantissa acq lag mantissa track lag exponent acq lag exponent track zero lag lead gain mux acc load upper/lower acc limits lag serial output formatter sof sofsync mid and end symbol samples i mid i end q mid q end symbol track loop filter r e g data decision transition detect transition mid-point mux ? ?1 ? mux + accumulator + mux lag gain + error accum. transition mid-point mux mux mux error invert invert sampling error reg limit shift shift - register enable rate ! = symbol rate blank = clk rate ! rail ! figure 11. symbol tracking reg to p interface HSP50210 3-16 sampling error detector the sampling error detector is a decision based error detector which determines sampling errors on both the i and q processing paths. the detector assumes that it is fed with samples of the baseband waveform taken in the middle of the symbol period (mid-symbol sample) and between symbols (end-symbol sample) as shown in figure 12. the sampling error is a measure of how far the mid-symbol sample is from the symbol transition mid-point. the transition mid-point is half way between two symbol decisions. the detector makes symbol decisions by comparing the end-symbol samples against a selectable threshold set (see modulation order select bits 9-10 in table 28). the error term is generated by subtracting the mid- symbol sample from the transition mid-point. the sign of the error term is negated for negatively sloped symbol transitions. if no symbol transitions are detected the error detector output is zeroed. errors on both the i and q processing paths are summed and divided by two if double rail error detection is selected (see symbol tracking con?uration control register, bit 8: table 28). the sampling error detector provides an error accumulator to compensate for the processing rate of the loop ?ter. the error detector generates outputs at the symbol rate, but the loop ?ter can only accept inputs every eight f clk clocks. thus, if the symbol rate is faster than 1/8 clk, the error accumulator should be used to accumulate the error until the loop ?ter is ready for a new input. if the error accumulator is not used when the symbol rate exceeds 1/8 clk, some error outputs will be missed. for example, if f clk = 40mhz, then error accumulation is required for symbol rates greater than 5 msps (f clk /8). note: the loop ?ter lead gain term must be scaled accordingly if the accumulator is used. symbol tracking loop filter the symbol tracking loop filter is a second order lead/lag filter. the sampling error is weighted by the lag gain and accumulated to give the integral response (see figure 11). the lag accumulator output is summed with the sampling error weighted by the lead gain. the result is a frequency term which is output serially, via the sof output, to the nco/vco controlling the baseband sample rate (see serial output section). in basic configurations, the sof output of the HSP50210 is connected to the sof input of the hsp50110. two sets of registers are provided to store the loop gain parameters associated with acquisition and tracking. the appropriate loop gain parameters are selected manually via the microprocessor interface or automatically via the carrier lock detector. the loop ?ter s lead and lag gain terms are represented as a mantissa and exponent. the mantissa is a 4-bit value which weights the loop ?ter input from 1.0 to 1.9375. the exponent de?es a shift factor that provides additional weighting from 2 -1 to 2 -32 . together the loop gain mantissa and exponent provide a gain range between 2 -32 and ~ 1.0 as given by, lead/lag gain = (1.0+m*2 -4 )*2 -(32 -e) (eq. 10) where m = a 4-bit binary number from 0 to 15, and e is a 5-bit binary value ranging from 0 to 31. for example, if m = 0101 and e = 00110, the gain = 1.3125*2 -26 . they are stored in the control registers described in table 31 and table 32. a limiter is provided on the lag accumulator output to keep the baseband sample rate within a user defined range (see table 29 and table 30). if the lag accumulator exceeds either the upper or lower limit, the accumulator is loaded with the limit. for additional loop filter control, the loop filter output can be frozen by asserting the fz_st pin which null the sampling error term into the loop filter. the lag accumulator can be initialized to a particular value and can be read via the microprocessor interface as described in the section ?eading from the microprocessor interface? and table 33. the symbol tracking loop filter bit weighting is identical to the carrier tracking loop bit weighting, shown in figures 9 and 10. soft decision slicer the soft decision slicer encodes the i/q end-symbol samples into 3-bit soft decisions. the input to the slicer is assumed to be a bi-polar (2ary) baseband signal representing encoded values of either ??or ?? the most signi?ant bit of the 3-bit soft decision represents a hard decision with respect to the mid-point between the expected symbol values. the 2 lsbs represent a level of con?ence in the decision. they are determined by comparing the magnitude of the slicer input to multiples (1x, 2x, and 3x) of a programmable soft decision threshold (see figure 13). x x x sampling error end-symbol sample expected symbol levels x x figure 12. tracking error associated with baseband sampling on either i or q rail (bpsk/qpsk) transition midpoint mid-symbol sample x HSP50210 3-17 the soft decision threshold represents a range of magnitude values from 0.0 to ~ 0.5. note: since the input to the slicer has a range of 0.0 to ~ 1.0, the threshold setting should be set to less than 1.0/3 = 0.33. this avoids saturation. the slicer decisions are output in either a two s complement or sign/magnitude format (see soft decision slicer configuration control register, bit 7: table 40). the slicer input to output mapping for a range of input magnitudes is given in table 7. for example, a negative input to the slicer whose magnitude is greater than twice the programmable threshold but less than 3x the threshold would produce a sign/magnitude output of 110 (binary). the i and q inputs to the slicer are encoded into 3-bit soft decisions isoft(2-0) and qsoft(3-0). these signals are routed to the outa(9-4) outputs by the output configuration control register selector bits 0-3 (see table 42). carrier phase error detector the carrier phase error is computed by removing the phase modulation from the phase output of the cartesian to polar converter. to remove the modulation, the phase term is rotated and multiplied (modulo 2 ) to fold the phase error into an arc centered about 0 o but encompasses the whole plane, as shown in figure 14. the phase rotation is performed by adding a 4-bit two s complement phase offset (resolution 22.5 o ) to the 4 msbs of the 8-bit phase term. the multiplication is performed by left shifting the result from 0-3 positions with the msb s discarded and zeros inserted into the lsb s. for example, carrier phase error produces i/q constellation points which are rotated from the expected constellation points as shown in figure 14. by adding an offset of 45 o (0010 0000 binary) and multiplying by 4 (left shift by two positions) the phase modulation is removed, and the error is folded into a 90 o arc centered at 0 o . the left axis represents a decision boundary of 45 o c, implying the vertical axis is 22.5 o as shown in figure 14. the phase offset and shift factors required for different psk orders is given in table 8. configuration of the carrier phase error detector is done via the carrier phase error detector control register, bits 0-5, (see table 17). the phase error term may be selected for output via the output selector configuration control register, bits 0-3 (see table 42). probability density ? ? function threshold 2x threshold 3x threshold threshold 2x threshold 3x threshold stronger weaker stronger weaker hard decision threshold 0.0 0.5 -0.5 ??decision ??decision figure 13. overlay of the hard/soft decision thresholds on the symbol probability density functions (pdfs) for bpsk/qpsk signals) fs 0 1/3 1/2 -fs threshold msb-1 msb-1 1/2 1/3 threshold msb msb msb-1 msb-1 table 7. slicer input to output mapping signal input polarity slicer input magnitude relative to sign/magnitude output two? complement output 1x threshold 2x threshold 3x threshold +>>>011011 +>> 010 010 +> < 001 001 + < < 000 000 - < < 100 111 -> < 101 110 ->> 110 101 - > > > 111 100 HSP50210 3-18 in applications where phase error terms are generated faster than the processing rate of the carrier loop filter, an error accumulator is provided to accumulate errors until the loop ?ter is ready for a new input. phase error terms are generated at the rate i/q samples are input to the cartesian to polar converter. however, the carrier loop filter can not accept new input faster than clk/6 since six clk(f clk ) clock edges are required to complete its processing cycle. if the error accumulator is not used and the i/q sample rate exceeds clk/6, error terms will be missed. note: the carrier phase error terms input to the loop ?ter are only generated from the end-symbol samples when the output of the i&d ?ter is selected for input to the cartesian-to-polar converter. note: the loop ?ter lead gain term must be scaled accordingly if the accumulator is used. carrier loop filter the carrier loop filter is second order lead/lag ?ter as shown in figure 14. the loop ?ter is similar to the symbol tracking loop filter except for the additional terms from the afc loop filter and the frequency sweep block. the output of the lag accumulator is summed with the weighted phase error term on the lead path to produce a frequency control term. the carrier loop filter is con?ured for operation by the control registers described in tables 20 to 27. the carrier tracking loop is closed by using the loop ?ter output to control the nco or vco used to down convert the channel of interest. in basic con?urations, the frequency correction term controls the synthesizer nco in the hsp50110 digital quadrature tuner via the cof and cofsync pins of the HSP50210 |